Developed the DR2/TESLA Main Processor Board (MPB) and Other DR2 & TESLA Boards

I used to say, “those aren’t electrons flowing on the MPB, those are my blood cells!”   In a philosophical sense, it was true – the development of the MPB drained me like no other project effort, before or since.

With multiple processors on board – 2 x PIC 16C MCUs (one for front panel keyboard, one for watchdog processor), a TI TMS320C32 DSP, an Altera Flex 10K FPGA, an Altera MAX 7000 CPLD, 3 x National Semiconductor LM12458 microsequenced ADCs, and a Motorola MC68HC11 MCU for IRIG processing, 3 x NS16550 FIFO UARTs, and a 16 bit PC-104 bus connection, it was quite busy.  An X86-based PC-104 card was mounted on top of the MPB – lower powered on the DR2, but much more powerful model on the TESLA.

The concept was that sifting, sorting, compression, and decision making was done on the DSP, where memory was expensive but calculations were easy.  The resultant data was streamed through a high-speed DSP-to-X86 FIFO, where the X86 DMA’d it into main memory and stored it to disk.  The X86 was used because its memory was plentiful and inexpensive, and disk I/O was fast and easy.

The other boards in the system weren’t as complex, but were just as important.  The DR2 AIB, mounted on the bottom of the chassis, had up to 18 miniature PCB-mount instrumentation transformers on it – CTs or PTs, depending on the application – and analog processing to transfer to the ADCs on the MPB.  The TESLA AIB was mounted on the rear of the chassis, had more channels but was less sophisticated – non isolated +/- 2.5V (nominal) input.  The DR2 and TESLA each had their own interpretation of digital I/O – DR2 with high current relay outputs, and dedicated ultra reliable digital inputs, and the TESLA with fewer and lower level outputs and simpler digital inputs.

The front panel of the DR2 had a 2 line x 24 character FIP display, a small keyboard, and several indicator LEDs, including a large bright red “Target” LED, as is expected on a relay.  The TESLA front panel had the smaller LEDs only.

I established the bus structure and pin-outs for all the I/O.  The front panel and digital I/O were intentionally designed to be interchangeable, with the intention of future mixed mode configuration, or expansion.  Although some of the buses had extra connections (front panel serial port, for instance), this was kept to the ends of the connectors, so combining and splitting ribbon cables would be relatively straightforward.  This was very well documented in extensive spreadsheets, which clearly showed connections and levels.

The memory and I/O maps of the processors was also documented in spreadsheets, with well defined bit states and clearly defined defaults.

Later, I wrote an exhaustive 70+ page programming guide to the MPB, which outlined all its features, how each processor interacted, the resources used, assumptions in programming, and how to compose images for execution.