Developed the Conviron Integrated Logger Controller (ILC) Card

The CMP3000 has a very sophisticated network operating over isolated RS-422 signals in a ring-bus arrangement.  Each controller has a bypass relay which would heal the ring-bus in the event of controller or communication board failure.  The Zilog Z8530 Serial Communications Controller (SCC) chip was used to talk HDLC on the ring-bus.

The master of the network was the CMP3300 Data Logger Processor (DLP), which was essentially a hot-rodded CMP3000 controller with different programming.  It could manage and control up to 96 CMP3000 controllers on its loop.

To enhance and extend its function, the DLP had a serial port which could be connected to the Host Computer, an IBM PC running QNX.  The Host computer could be connected to 3 DLPs, allowing it to manage many more controllers.

Being a general purpose PC running QNX, the Host Computer was able to schedule changes, log all kinds of data, display graphs, and export data to other media (think: floppy disks!).

There came a time when the DLP just seemed clunky.  So, I was asked to create the Loop Control Card (LCC), which would mount directly into the IBM PC chassis and replace the DLP.  It would be able to control 3 loops of controllers, and have embedded on-board alarm contacts.

By then, the PC of choice was the AT, and Vansco actually was making its own labelled computers, based on components purchased overseas.  However, the LCC was designed for the XT bus for maximum compatibility.

The heart of the board was a NEC V25 processor, high-speed (well, for the time) SRAM, and a few PLDs, where I implemented a pseudo-dual-port RAM for control and data transfer.  Internal bus faults occurred periodically, which proved almost impossible to track down without the right test equipment.  Finally, management went and bought a very expensive (at he time) Fluke/Phillips PM3585/90 logic analyzer, which I proceeded to load up to the maximum, using its dual timing & state analysis to great advantage.  In the end, the V25 was every once in a while stealing an extra clock cycle for its prefetch queue, causing a bus timeout.  The PC bus specification wouldn’t let me stretch it any further.  I was able to rework the logic and make it all come together.  You gotta have the right tools!

PM3585 Logic Analyzer